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240pin DDR3 SDRAM Unbuffered DIMMs
DDR3 SDRAM Unbuffered DIMMs Based on 1Gb B version
HMT164U6BFR6C HMT112U6BFR8C HMT112U7BFR8C HMT125U6BFR8C HMT125U7BFR8C
** Contents are subject to change without prior notice.
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HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
Revision History
Revision No. 0.01 0.02 0.1 History Initial draft for internal review Added IDD Specification Updated IDD Specification Draft Date Dec. 2008 Feb. 2009 Apr. 2009 Remark Preliminary Preliminary
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Table of Contents
1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(1Rank of x8) 3.3 1GB, 128Mx72 ECC Module(1Rank of x8) 3.4 2GB, 256Mx64 Module(2Rank of x8) 3.5 2GB, 256Mx72 ECC Module(2Rank of x8) 4. Address Mirroring Feature 4.1 DRAM Pin Wiring for Mirroring 5. Absolute Maximum Ratings 5.1 Absolute Maximum DC Ratings 5.2 Operating Temperature Range 6. AC & DC Operating Conditions 6.1 Recommended DC Operating Conditions 6.2 DC & AC Logic Input Levels 6.2.1 For Single-ended Signals 6.2.2 For Differential Signals 6.2.3 Differential Input Cross Point 6.3 Slew Rate Definition 6.3.1 For Ended Input Signals 6.3.2 For Differential Input Signals 6.4 DC & AC Output Buffer Levels 6.4.1 Single Ended DC & AC Output Levels 6.4.2 Differential DC & AC Output Levels 6.4.3 Single Ended Output Slew Rate 6.4.4 Differential Ended Output Slew Rate 6.5 Overshoot/Undershoot Specification 6.6 Input/Output Capacitance & AC Parametrics 6.7 IDD Specifications & Measurement Conditions 7. Electrical Characteristics and AC Timing 7.1 Refresh Parameters by Device Density 7.2 DDR3 Standard speed bins and AC para 8. DIMM Outline Diagram 8.1 512MB, 64Mx64 Module(1Rankx16) 8.2 1GB, 128Mx64 Module(1Rank of x8) 8.3 1GB, 128Mx72 ECC Module(1Rank of x8) 8.4 2GB, 256Mx64 Module(2Rank of x8) 8.5 2GB, 256Mx72 ECC Module(2Rank of x8)
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1. Description
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb B version. DDR3 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 1Gb B ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
* VDD=VDDQ=1.5V * VDDSPD=3.3V to 3.6V * Fully differential clock inputs (CK, /CK) operation * Differential Data Strobe (DQS, /DQS) * On chip DLL align DQ, DQS and /DQS transition with CK transition * DM masks write data-in at the both rising and falling edges of the data strobe * All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock * Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported * Programmable additive latency 0, CL-1, and CL-2 sup ported * Programmable CAS Write latency (CWL) = 5, 6, 7, 8 * Programmable burst length 4/8 with both nibble sequential and interleave mode * BL switch on the fly * 8banks * 8K refresh cycles /64ms * DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls * Driver strength selected by EMRS * Dynamic On Die Termination supported * Asynchronous RESET pin supported * ZQ calibration supported * TDQS (Termination Data Strobe) supported (x8 only) * Write Levelization supported * Auto Self Refresh supported * On Die Thermal Sensor supported (JEDEC optional)
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HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
1.1.2 Ordering Information
# of DRAMs 4 8 9 16 18 # of ranks 1 1 1 2 2
Part Name HMT164U6BFR6C - G7/H9 HMT112U6BFR8C - G7/H9 HMT112U7BFR8C - G7/H9 HMT125U6BFR8C - G7/H9 HMT125U7BFR8C - G7/H9
Density 512MB 1GB 1GB 2GB 2GB
Org. 64Mx64 128Mx64 128Mx72 256Mx64 256Mx72
Materials Halogen-free Halogen-free Halogen-free Halogen-free Halogen-free
ECC None None ECC None ECC
TS No No Yes No Yes
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1.2 Speed Grade & Key Parameters
MT/S Grade tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) CL-tRCD-tRP 1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 Unit -H9 1.5 9 13.5 13.5 36 49.5 9-9-9 ns tCK ns ns ns ns tCK
1.3 Address Table
512MB Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device 64M x 64 8K/64ms A0-A12 A0-A9 BA0-BA2 2KB 1 4 1GB 128M x 64 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 8 1GB 128M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 9 2GB 256M x 64 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 16 2GB 256M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 18
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2. Pin Architecture
2.1 Pin Definition
Pin Name A0-A13 BA0-BA2 RAS CAS WE S0-S1 CKE0-CKE1 ODT0-ODT1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0-DQS8 DM0-DM8 CK0-CK1 CK0-CK1 Description SDRAM address bus SDRAM bank select SDRAM row address strobe SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) SDRAM data masks/high data strobes (x8-based x72 DIMMs) SDRAM clocks (positive line of differential pair) SDRAM clocks (negative line of differential pair) Pin Name SCL SDA SA0-SA2 VDD* VDDQ* VREFDQ VREFCA VSS VDDSPD NC TEST RESET VTT RFU Description I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C slave address select for EEPROM SDRAM core power supply SDRAM I/O Driver power supply SDRAM I/O reference supply SDRAM command/address reference supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) Memory bus analysis tools (unused on memory DIMMS) Set DRAMs to Known State SDRAM I/O termination supply Reserved for future use -
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
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2.2 Input/Output Functional Description
Symbol CK0-CK1 CK0-CK1 Type Polarity Differential crossing Function CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing). Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks. RAS, CAS, and WE (ALONG WITH S) define the command being entered. When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming this function is enabled in the Mode Register 1 (MR1). Reference voltage for SSTL15 I/O inputs. Reference voltage for SSTL 15 command/address inputs. Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. -- Selects which SDRAM bank of eight is activated. During a Bank Activate command cycle, Address input defines the row address (RA0-RA15). During a Read or Write command cycle, Address input defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped). Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules.
SSTL
CKE0-CKE1
SSTL
Active High
S0-S1
SSTL
Active Low
RAS, CAS, WE ODT0-ODT1 VREFDQ VREFCA VDDQ BA0-BA2
SSTL SSTL Supply Supply Supply SSTL
Active Low Active High
A0-A13
SSTL
--
DQ0-DQ63, CB0-CB7
SSTL
--
DM0-DM8
SSTL
Active High
VDD, VSS
Supply
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Symbol DQS0-DQS8 DQS0-DQS8 SA0-SA2
Type SSTL
Polarity Differential crossing --
Function Data strobe for input and output data. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pullup on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 3.0V to 3.6V.
SDA
--
SCL
--
VDDSPD
Supply
2.3 Pin Assignment
Front Side(left 1-60) Pin x64 # Non-ECC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VREFDQ VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 x72 ECC VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 Back Side(right 121-180) Pin x64 # Non-ECC VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 x72 ECC VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS Front Side(left 61-120) Back Side(right 181-240) Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 x64 Non-ECC A2 VDD CK1 CK1 VDD VDD VREFCA NC VDD A10 BA02 VDD WE CAS VDD S1 x72 ECC A2 VDD CK1 CK1 VDD VDD VREFCA NC VDD A10 BA02 VDD WE CAS VDD S1 Pin # 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 x64 Non-ECC A1 VDD VDD CK0 CK0 VDD NC A0 VDD BA12 VDD RAS S0 VDD ODT0 A13 x72 ECC A1 VDD VDD CK0 CK0 VDD NC A0 VDD BA12 VDD RAS S0 VDD ODT0 A13
VREFDQ 121
NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses.
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Front Side(left 1-60) Pin x64 # Non-ECC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS x72 ECC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS
Back Side(right 121-180) Pin x64 # Non-ECC 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS DM8 NC VSS NC NC VSS NC x72 ECC DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC
Front Side(left 61-120) Back Side(right 181-240) Pin # 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 x64 Non-ECC ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS x72 ECC ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS Pin # 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 x64 Non-ECC VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 x72 ECC VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60
NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses.
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Front Side(left 1-60) Pin x64 # Non-ECC 48 49 50 51 52 53 54 55 56 57 58 59 60 NC KEY NC CKE0 VDD BA2 NC VDD All A72 VDD A52 A42 VDD NC CKE0 VDD BA2 NC VDD All A72 VDD A52 A42 VDD x72 ECC NC
Back Side(right 121-180) Pin x64 # Non-ECC 168 169 170 171 172 173 174 175 176 177 178 179 180 Reset KEY CKE1/NC VDD NC NC VDD A12 A9 VDD A82 A62 VDD A32 CKE1/NC VDD NC NC VDD A12 A9 VDD A82 A62 VDD A32 x72 ECC Reset
Front Side(left 61-120) Back Side(right 181-240) Pin # 108 109 110 111 112 113 114 115 116 117 118 119 120 x64 Non-ECC DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT x72 ECC DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Pin # 228 229 230 231 232 233 234 235 236 237 238 239 240 x64 Non-ECC DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT x72 ECC DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT
NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses.
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3. Functional Block Diagram
3.1 512MB, 64Mx64 Module(1Rank of x16)
S0 DQS0 DQS0 DM0
CS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
D0
DQS4 DQS4 DM4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
D2
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS5 DQS5 DM5
ZQ
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
ZQ
DQS2 DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS CS D1
DQS6 DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS CS D3
DQS3 DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
UDQS CS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
DQS7 DQS7 DM7
ZQ
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
UDQS CS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
ZQ
Serial PD SCL BA0-BA2 A0-A14 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET BA0-BA2: SDRAMs D0-D3 A0-A14: SDRAMs D0-D3 RAS: SDRAMs D0-D3 CAS: SDRAMs D0-D3 CKE: SDRAMs D0-D3 WE: SDRAMs D0-D3 ODT: SDRAMs D0-D3 CK: SDRAMs D0-D3 CK: SDRAMs D0-D3 RESET:SDRAMs D0-D3 WP A0 SA0 A1 SA1 A2 SA2 SDA
VDDSPD VDD/VDDQ VREFDQ VSS VREFCA
SPD D0-D3 D0-D3 D0-D3 D0-D3
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. The pair CK1 and CK1# is terminated in 75ohm but is not used on the module. 6. A15 is not routed on the module. 7. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 8. One SPD exists per module.
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3.2 1GB, 128Mx64 Module(1Rank of x8)
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS4 DQS4 DM4
I/O I/O I/O I/O I/O I/O I/O I/O DM CS DQS DQS 0 1 D0 2 3 4 5 6 ZQ 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
D4
ZQ
DQS1 DQS1 DM1
DQS5 DQS5 DM5
DQS2 DQS2 DM2
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DM CS DQS DQS I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7
DQS6 DQS6 DM6
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D5
ZQ
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
I/O I/O I/O I/O I/O I/O I/O I/O
DM CS DQS DQS 0 1 D2 2 3 4 5 6 7 ZQ
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D6
ZQ
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D7
ZQ
Serial PD WP A0 SDA A1 SA1 A2 SA2
SCL
BA0-BA2 A0-A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET
BA0-BA2: SDRAMs D0-D7 A0-A15: SDRAMs D0-D7 RAS: SDRAMs D0-D7 CAS: SDRAMs D0-D7 CKE: SDRAMs D0-D7 WE: SDRAMs D0-D7 ODT: SDRAMs D0-D7 CK: SDRAMs D0-D7 CK: SDRAMs D0-D7 RESET:SDRAMs D0-D7
SA0
VDDSPD VDD/VDDQ VREFDQ VSS VREFCA
SPD D0-D7 D0-D7 D0-D7 D0-D7
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. Refer to Section 3.1 of this document for details on address mirroring. 6. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 7. One SPD exists per module.
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3.3 1GB, 128Mx72 Module(1Rank of x8)
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS4 DQS4 DM4
CS DQS DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
ZQ
DQS1 DQS1 DM1
DQS5 DQS5 DM5
CS DQS DQS
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D4
ZQ
DQS2 DQS2 DM2
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
ZQ
DQS6 DQS6 DM6
CS DQS DQS
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D5
ZQ
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
ZQ
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D6
ZQ
DQS8 DQS8 DM8
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D3
ZQ
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS DQS
D7
ZQ
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
SPD(TS integrated) SCL
D8
EVENT
ZQ
EVENT
A0 SA0
SDA A1 SA1
A2
SA2
BA0-BA2 A0-A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET
BA0-BA2: SDRAMs D0-D8 A0-A15: SDRAMs D0-D8 VDDSPD RAS: SDRAMs D0-D8 VDD/VDDQ CAS: SDRAMs D0-D8 CKE: SDRAMs D0-D8 VREFDQ WE: SDRAMs D0-D8 VSS ODT: SDRAMs D0-D8 CK: SDRAMs D0-D8 VREFCA CK: SDRAMs D0-D8 RESET:SDRAMs D0-D8
SPD D0-D8 D0-D8 D0-D8 D0-D8
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module.
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S0 DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
S1 DQS4 DQS4 DM4
DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D12 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DQS5 DQS5 DM5
DM CS DQS DQS I/O 0 I/O 1 D9 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
ZQ
ZQ
CS DQS DQS
D1
DQS2 DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQS6 DQS6 DM6
ZQ
DM CS DQS DQS I/O 0 I/O 1 D13 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
CS DQS DQS
D2
DQS3 DQS3 DM3
ZQ
DM CS DQS DQS I/O 0 I/O 1 D10 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM CS DQS DQS I/O 0 I/O 1 D14 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DQS7 DQS7 DM7
DM CS DQS DQS I/O 0 I/O 1 D11 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D3
ZQ
ZQ
ZQ
Serial PD BA0-BA2 A0-A15 CKE1 CKE0 RAS CAS WE ODT0 ODT1 CK0 CK0 CK1 CK1 BA0-BA2: SDRAMs D0-D15 SCL A0-A15: SDRAMs D0-D15 WP CKE: SDRAMs D8-D15 A0 CKE: SDRAMs D0-D7 SA0 RAS: SDRAMs D0-D15 CAS: SDRAMs D0-D15 VDDSPD WE: SDRAMs D0-D15 VDD/VDDQ ODT: SDRAMs D0-D7 VREFDQ ODT: SDRAMs D8-D15 CK: SDRAMs D0-D7 VSS CK: SDRAMs D0-D7 VREFCA CK: SDRAMs D8-D15 CK: SDRAMs D8-D15 SDA A1 SA1
A2
SA2 SPD D0-D15 D0-D15 D0-D15 D0-D15
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram. 4. Refer to Section 3.1 of this document for details on address mirroring. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module.
RESET
RESET:SDRAMs D0-D3
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DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
S1 DQS4 DQS4 DM4
DM CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
D9
ZQ
DQS1 DQS1 DM1
DQS5 DQS5 DM5
CS DQS DQS
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D13
ZQ
DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D1
DQS2 DQS2 DM2
ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D10
ZQ
DQS6 DQS6 DM6
CS DQS DQS
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D14
ZQ
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DM CS DQS DQS I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D11
ZQ
DQS7 DQS7 DM7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D15
ZQ
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
DQS8 DQS8 DM8
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
ZQ
ZQ
SCL
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS DQS
D16
ZQ
SPD
VDDSPD
SPD(TS integrated)
DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS
VDD/VDDQ
D0-D17 D0-D17 D0-D17 D0-D17
EVENT
EVENT
A0 SA0
SDA A1 SA1
VREFDQ Vss VREFCA
D17
A2
SA2
ZQ
ZQ
ODT: SDRAMs D0-D8 ODT: SDRAMs D9-D17 CK: SDRAMs D0-D8 CK: SDRAMs D0-D8 CK: SDRAMs D9-D17 CK: SDRAMs D9-D17 RESET:SDRAMs D0-D17
BA0-BA2 A0-A15 CKE0 CKE1 RAS CAS WE
BA0-BA2: SDRAMs D0-D17 A0-A15: SDRAMs D0-D17 CKE: SDRAMs D0-D8 CKE: SDRAMs D9-D17 RAS: SDRAMs D0-D17 CAS: SDRAMs D0-D17 WE: SDRAMs D0-D17
ODT0 ODT1 CK0 CK0 CK1 CK1 RESET
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM/DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to Section 3.1 of this document for details on address mirroring. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module.
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4. Address Mirroring Feature
There is a via grid located under the SDRAMs for wiring the CA signals (address, bank address, command, and control lines) to the SDRAM pins. The length of the traces from the via to the SDRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.The pins on the SDRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 SDRAM pins are wired straight, with no mismatch between the connector pin assignment and the SDRAM pin assignment. Some of the Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.
4.1 DRAM Pin Wiring for Mirroring
Connector Pin A3 A4 A5 A6 A7 A8 BA0 BA1 SDRAM Pin Rank 0 A3 A4 A5 A6 A7 A8 BA0 BA1 The table 4.1 illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the SDRAM pins, is obviously shorter. The via grid is smaller as well. Rank 1 A4 A3 A6 A5 A8 A7 BA1 BA0
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No Mirroring
Mirroring
< Figure 4.1: Wiring Differences for Mirrored and Non-Mirrored Addresses >
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.
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5. ABSOLUTE MAXIMUM RATINGS
5.1 Absolute Maximum DC Ratings
Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V ,2 Notes ,3 ,3
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
5.2 DRAM Component Operating Temperature Range
Symbol TOPER Parameter Normal Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units Notes ,2 1,3
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85... and 95... case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. (This double refresh requirement may not apply for some devices.) It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/ or the DIMM SPD for option avail ability. b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
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6. AC & DC Operating Conditions
6.1 Recommended DC Operating Conditions
Rating Min. 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575
Symbol VDD VDDQ
Parameter Supply Voltage Supply Voltage for Output
Units V V
Notes 1,2 1,2
1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD abd VDDQ tied together.
6.2 DC & AC Logic Input Levels
6.2.1 DC & AC Logic Input Levels for Single-Ended Signals DDR3-1066, DDR3-1333 Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VRefDQ(DC) VRefCA(DC) VTT Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low Reference Voltage for DQ, DM inputs Reference Voltage for ADD, CMD inputs Termination voltage for DQ, DQS outputs 0.49 * VDD 0.49 * VDD VDDQ/2 - TBD Vref + 0.175 Vref + 0.100 Max Vref - 0.100 Vref - 0.175 0.51 * VDD 0.51 * VDD VDDQ/2 + TBD V V V V V V V 1, 2 1, 2 1, 2 1, 2 3, 4 3, 4 Unit Notes
1. For DQ and DM, Vref = VrefDQ. For input ony pins except RESET#, Vref = VrefCA. 2. The "t.b.d." entries might change based on overshoot and undershoot specification. 3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). For reference: approx. VDD/2 +/- 15 mV. The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure 6.2.1. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 1. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than +/- 1% VDD.
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voltage
VDD
VRef ac-noise VRef(DC)
VRef(t) VRef(DC)max VDD/2 VRef(DC)min
VSS
time
< Figure 6.2.1: Illustration of Vref(DC) tolerance and Vref AC-noise limits >
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef(DC), as defined in Figure 6.2.1 This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
6.2.2 DC & AC Logic Input Levels for Differential Signals
DDR3-1066, DDR3-1333 Min + 0.200 Max - 0.200
Symbol VIHdiff VILdiff Note1:
Parameter Differential input logic high Differential input logic low
Unit V V
Notes 1 1
Refer to "Overshoot and Undershoot Specification section 6.5 on 26 page
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6.2.3 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3 The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS.
VDD CK#, DQS#
VIX VDD/2 VIX VIX
CK, DQS VSS
< Figure 6.2.3 Vix Definition >
DDR3-1066, DDR3-1333 Symbol Parameter Min VIX Differential Input Cross Point Voltage relative to VDD/2 - 150 Max + 150 mV Unit Notes
< Table 6.2.3: Cross point voltage for differential input signals (CK, DQS) >
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6.3 Slew Rate Definitions
6.3.1 For Single Ended Input Signals
- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL(AC)max. - Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VRef. Measured Min Vref Vref VIL(DC)max VIH(DC)min Max VIH(AC)min VIL(AC)max Vref Vref
Description Input slew rate for rising edge Input slew rate for falling edge Input slew rate for rising edge Input slew rate for falling edge
Defined by VIH(AC)min-Vref Delta TRS Vref-VIL(AC)max Delta TFS Vref-VIL(DC)max Delta TFH VIH(DC)min-Vref Delta TRH
Applicable for
Setup (tIS, tDS)
Hold (tIH, tDH)
< Table 6.3.1: Single-Ended Input Slew Rate Definition >
Part A: Set up Delta TRS Single Ended input Voltage(DQ,ADD, CMD) vIH(AC)min vIH(DC)min
vRefDQ or vRefCA
vIL(DC)max vIL(AC)max
Delta TFS
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P a rt B : H o ld D e lta T R H Single Ended input Voltage(DQ,ADD, CMD) v IH (A C )m in
v IH (D C )m in
v R e fD Q o r v R e fC A
v IL (D C )m a x v IL (A C )m a x D e lta T F H
< Figure 6.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >
6.3.2 Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table and Figure . Measured Min VILdiffmax VIHdiffmin Max VIHdiffmin VILdiffmax
Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Note:
Defined by VIHdiffmin-VILdiffmax DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
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Differential Input Voltage (i.e. DQS-DQS; CK-CK)
D e lta T R d iff vIH d iffm in
0
vILd iffm a x D e lta T F d iff
< Figure 6.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >
6.4 DC & AC Output Buffer Levels
6.4.1 Single Ended DC & AC Output Levels
Below table shows the output levels used for measurements of single ended signals. Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level DDR3-1066, 1333 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ Unit V V V V 1 Notes
VTT - 0.1 x VDDQ V 1 (for output SR) 1. The swing of 1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ / 2.
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6.4.2 Differential DC & AC Output Levels
Below table shows the output levels used for measurements of differential signals. Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) DDR3-1066, 1333 + 0.2 x VDDQ Unit V Notes 1
AC differential output low - 0.2 x VDDQ V 1 measurement level (for output SR) 1. The swing of ae 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swingwith a driver impedance of 40Y and an effective test load of 25Y to VTT = VDDQ/2 at each of the differential output
6.4.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3. Measured From VOL(AC) VOH(AC) To VOH(AC) VOL(AC)
Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Note:
Defined by VOH(AC)-VOL(AC) DeltaTRse VOH(AC)-VOL(AC) DeltaTFse
Output slew rate is verified by design and characterization, and may not be subject to production test.
D e lt a T R s e Single Ended Output Voltage(l.e.DQ)
vO H (A C )
V
vO L(A C )
D e lt a T F s e
< Figure 6.4.3: Single Ended Output Slew Rate Definition >
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Parameter Single-ended Output Slew Rate
Symbol SRQse
DDR3-1066 Min 2.5 Max 5 2.5
DDR3-1333 Min Max 5
Units V/ns
*** Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) For Ron = RZQ/7 setting < Table 6.4.3: Output Slew Rate (single-ended) >
6.4.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below Table and Figure 6.4.4 Measured From VOLdiff(AC) VOHdiff(AC) To VOHdiff(AC) VOLdiff(AC)
Description Differential output slew rate for rising edge Differential output slew rate for falling edge
Defined by VOHdiff(AC)-VOLdiff(AC) DeltaTRdiff VOHdiff(AC)-VOLdiff(AC) DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Voltage(i.e. DQS-DQS)
D e lta T R d iff v O H d iff(A C )
O
v O L d iff(A C ) D e lta T F d iff
< Figure 6.4.4: Differential Output Slew Rate Definition >
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DDR3-1066 Parameter Differential Output Slew Rate Symbol Min SRQdiff 5
DDR3-1333 Min 5
Max
10
Max
10
Units
V/ns
***Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting < Table 6.6.4: Differential Output Slew Rate >
6.5 Overshoot and Undershoot Specifications
6.5.1 Address and Control Overshoot and Undershoot Specifications
Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure) Specification DDR3-1066 0.4V 0.4V 0.5 V-ns 0.5 V-ns DDR3-1333 0.4V 0.4V 0.4 V-ns 0.4 V-ns
< Table 6.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins > < Figure 6.5.1: Address and Control Overshoot and Undershoot Definition >
Maximum Amplitude Overshoot Area
Volts (V)
VDD VSS
Undershoot Area Maximum Amplitude Time (ns)
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6.5.2 Clock,Data,Strobe and Mask Overshoot and Undershoot Specifications Specification DDR3-1066 0.4V 0.4V 0.19 V-ns 0.19 V-ns DDR3-1333 0.4V 0.4V 0.15 V-ns 0.15 V-ns
Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDDQ (See Figure) Maximum undershoot area below VSSQ (See Figure)
< Table 6.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask >
M a x im u m A m p litu d e O v e rsh o o t A re a
V o lts (V )
VDDQ VSSQ
U n d e rsh o o t A re a M a x im u m A m p litu d e T im e (n s) C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n
< Figure 6.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition >
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6.6 Pin Capacitance
Parameter Input/output capacitance (DQ, DM, DQS, DQS#, TDQS, TDQS#) Input capacitance, CK and CK# Input capacitance delta CK and CK# Input capacitance (All other input-only pins) Input capacitance delta, DQS and DQS# Input capacitance delta (All CTRL input-only pins) Input capacitance delta (All ADD/CMD input-only pins) Input/output capacitance delta (DQ, DM, DQS, DQS#) Notes: 1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic characterization of TDQS/TDQS# should be close as much as possible, Cio&Cdio requirement is applied (recommend deleting note or changing to "Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.") 2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)") with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK#. 5. The minimum CCK will be equal to the minimum CI. 6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. CTRL pins defined as ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#)) 9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#)) 12. Absolute value of CIO(DQS) - CIO(DQS#) Symbol CIO CCK CDCK CI CDDQS CDI_CTRL CDI_ADD_C
MD
DDR3-1066 Min 1.5 TBD 0 TBD 0 -0.5 -0.5 -0.5 Max 3.0 1.6 0.15 1.5 0.20 0.3 0.5 0.3
DDR3-1333 Min 1.5 TBD TBD TBD TBD TBD TBD TBD Max 2.5 TBD TBD TBD TBD TBD TBD TBD
Units Notes pF pF pF pF pF pF pF pF 1,2,3 2,3,5 2,3,4 2,3,6 2,3,12 2,3,7,8 2,3,9,1 0 2,3,11
CDIO
6.7 IDD Specifications(TCASE: 0 to 95oC)
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512MB, 64M x 64 U-DIMM: HMT164U6BFR6C Symbol DDR3 1066 DDR3 1333 Unit
IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
400 500 200 200 40 140 200 280 140 780 780 720 40 48 48 840
420 520 220 220 40 140 220 300 160 860 860 720 40 48 48 1040
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1GB, 128M x 64 U-DIMM: HMT112U6BFR8C Symbol DDR3 1066 DDR3 1333 Unit
IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
600 680 400 400 80 200 400 480 240 960 960 1360 80 96 96 1280
640 760 440 440 80 240 440 520 240 1080 1080 1360 80 96 96 1600
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
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1GB, 128M x 72 U-DIMM: HMT112U7BFR8C Symbol DDR3 1066 DDR3 1333 Unit
IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
675 765 450 450 90 225 450 540 270 1080 1080 1530 90 108 108 1440
720 855 495 495 90 270 495 585 270 1215 1215 1530 90 108 108 1800
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2GB, 256M x 64 U-DIMM: HMT125U6BFR8C Symbol DDR3 1066 DDR3 1333 Unit
IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
1000 1080 800 800 160 400 800 960 480 1360 1360 1760 160 192 192 1680
1080 1200 880 880 160 480 880 1040 480 1520 1520 1800 160 192 192 2040
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
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2GB, 256M x 72 U-DIMM: HMT125U7BFR8C Symbol DDR3 1066 DDR3 1333 Unit
IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
1125 1215 900 900 180 450 900 1080 540 1530 1530 1980 180 216 216 1890
1215 1350 990 990 180 540 990 1170 540 1710 1710 2025 180 216 216 2295
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
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6.7 IDD Measurement Conditionss
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. * IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
*
For IDD and IDDQ measurements, the following definitions apply: * * * * * * * "0" and "LOW" is defined as VIN <= VILAC(max). "1" and "HIGH" is defined as VIN >= VIHAC(max). "FLOATING" is defined as inputs are VREF - VDD/2. Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1 on Page 26. Basic IDD and IDDQ Measurement Conditions are described in Table 2 on page 26. Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 on page 30 through Table 10 on page 36. IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
* * *
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IDD
IDDQ (optional)
VDD
RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ
VDDQ
DDR3 SDRAM
DQS, DQS DQ, DM, TDQS, TDQS
RTT = 25 Ohm VDDQ/2
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above]
Application specific memory channel environment
IDDQ Test Load
Channel IO Power Simulation
IDDQ Simulation
IDDQ Simulation
Correction Channel IO Power Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK CL nRCD nRC nRAS nRP nFAW nRRD nRFC -512Mb nRFC-1 Gb nRFC- 2 Gb nRFC- 4 Gb nRFC- 8 Gb x4/x8 x16 x4/x8 x16 DDR3-800 5-5-5 2.5 5 5 20 15 5 16 20 4 4 36 44 64 120 140 DDR3-1066 7-7-7 1.875 7 7 27 20 7 20 27 4 6 48 59 86 160 187 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High IDD0 between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3 on page 30; Data IO: FLOATING; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3 on page 30); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3 on page 30 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: IDD1 High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4 on page 31; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4 on page 31); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4 page 31 Description
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Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2N Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5 on page 32 Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2NT Address, Bank Address Inputs: partially toggling according to Table 6 on page 32; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6 on page 32; Pattern Details: see Table 6 on page 32 IDDQ2NT Precharge Standby ODT IDDQ Current (optional Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current ) Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2P0 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2P1 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDDQ4R Operating Burst Read IDDQ Current (optional Same definition like for IDD4R, however measuring IDDQ current instead of IDD current )
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Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD3N Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5 on page 32 Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 7 on page 33; Data IO: IDD4R seamless read data burst with different data between one burst and the next one according to Table 7 on page 33; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7 on page 33); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7 on page 33 Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 8 on page 34; Data IO: IDD4W seamless read data burst with different data between one burst and the next one according to Table 8 on page 34; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8 on page 34); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8 on page 34 Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between IDD5B REF; Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 35; Data IO: FLOATING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 35); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9 on page 35
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Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Self-Refresh Current: Extended Temperature Range (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): ExtendIDD6ET ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Auto Self-Refresh Current (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6TC CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto SelfRefresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 26; BL: 8a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially togIDD7 gling according to Table 10 on page 36; Data IO: read data burst with different data between one burst and the next one according to Table 10 on page 36; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10 on page 36; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10 on page 36 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
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Table 3 - IDD0 Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1,2 3,4 ... nRAS ... 1*nRC+0
ACT D, D D, D PRE ACT PRE
0 1 1 0 0 0
0 0 1 0 0 0
1 0 1 1 1 1
1 0 1 0 1 0
0 0 0 0 0 0
0 0 0 0 00 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 F F
-
repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat pattern 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
Static High
toggling
... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
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Table 4 - IDD1 Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2
ACT D, D D, D
0 1 1
0 0 1
1 0 1
1 0 1
0 0 0
0 0 0
00 00 00
0 0 0
0 0 0
0 0 0
0000000 0 0011001 1 -
repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 0 0
repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE ACT D, D D, D 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 00 00 00 00 0 0 0 0 0 0 0 0 0 F F F 0 0 0 0 repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 F 0
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 F 0 repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
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Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2 3
D D D D
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2 3
D D D D
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
0000000 0
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
42
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2,3 4
RD D D,D RD D D,D
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
1 0 1 1 0 1
0 0 0 0 0 0
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
000000 00 001100 11 -
Static High
toggling
5 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
43
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
Table 8 - IDD4W Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2,3 4
WR D D,D WR D D,D
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
0 0 1 0 0 1
1 1 1 1 1 1
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
000000 00 001100 11 -
Static High
toggling
5 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
44
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
Table 9 - IDD5B Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0 1
0
1.2 3,4 5...8
REF D, D D, D
0 1 1
0 0 1
0 0 1
1 0 1
0 0 0
0 0 0
0 00 00
0 0 0
0 0 0
0 0 F
-
repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Static High
toggling
9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC-1
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
45
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
Table 10 - IDD7 Measurement-Loop Patterna) ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0]
A[10]
RAS
ODT
CKE
CAS
WE
CS
Datab)
0
1
2 3 4 5 6 7 8 Static High toggling 9
10
11
12 13 14 15 16 17 18 14
ACT 0 0 1 1 0 0 00 0 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 D 1 0 0 0 0 0 00 0 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F 0 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F 0 4*nRRD ... Assert and repeat above D Command until nFAW - 1, if necessary nFAW repeat Sub-Loop 0, but BA[2:0] = 4 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F 0 nFAW+4*nRRD ... Assert and repeat above D Command until 2* nFAW - 1, if necessary 2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 2&nFAW+2 Repeat above D Command until 2* nFAW + nRRD - 1 2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 2&nFAW+nRRD+ 2 Repeat above D Command until 2* nFAW + 2* nRRD - 1 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 0 00 0 0 0 0 2*nFAW+4*nRRD Assert and repeat above D Command until 3* nFAW - 1, if necessary 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 0 00 0 0 0 0 3*nFAW+4*nRRD Assert and repeat above D Command until 4* nFAW - 1, if necessary 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD
0
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
46
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
7. Electrical Characteristics and AC Timing
7.1 Refresh Parameters by Device Density
Parameter REF command to ACT or REF command time Average periodic refresh interval tREFI Symbol tRFC 512Mb 1Gb 2Gb 4Gb 8Gb Units
90
110
160
300
350
ns
0 xC < TCASE < 85 xC 85 xC < TCASE < 95 xC
7.8 3.9
7.8 3.9
7.8 3.9
7.8 3.9
7.8 3.9
us us
Rev. 0.1 / Apr 2009
47
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
7.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin
DDR3 1066 Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 Symbol min 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 < 2.5 < 2.5 3.3 DDR3-1066F 7-7-7 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns 1)2)3)4)6) 4) 1)2)3)6) 1)2)3)4) 4) 1)2)3)4) 4) 1)2)3) Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
CL = 6
CL = 7
CL = 8
Supported CL Settings Supported CWL Settings
nCK nCK
Rev. 0.1 / Apr 2009
48
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
DDR3 1333 Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5, 6 CWL = 7 CWL = 5, 6 CL = 10 CWL = 7 Symbol min 13.5 13.5 13.5 49.5 36
DDR3-1333H 9-9-9 max 20 -- -- -- 9 * tREFI Reserved Reserved 2.5 Reserved Reserved Reserved Reserved Reserved Reserved 1.875 Reserved Reserved 1.5 Reserved 1.5 (Optional) 6, 8, 9 5, 6, 7 <1.875 <1.875 < 2.5 3.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1,2,3,4,7 4 1,2,3,7 1,2,3,4,7 4 4 1,2,3,4,7 1,2,3,4 4 1,2,3,7 1,2,3,4 4 1,2,3,4 4 1,2,3 5 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
Rev. 0.1 / Apr 2009
49
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
*Speed Bin Table Notes* Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Notes: 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next `Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. `Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
Rev. 0.1 / Apr 2009
50
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
8. Dimm Outline Diagram
8.1 164Mx64 - HMT164U6BFR6C
Front
2.10 0.15 Min 1.45 4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50 Max R0.70 SPD 30.00
Back
Side
3.18
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27
1.00 0.10
0.3 0.15
0.35 0.05
3.80
0.3~1.0
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
51
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
8.2 128Mx64 - HMT112U6BFR8C
Front
2.10 0.15 Min 1.45 SPD 4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50 Max R0.70 30.00
Back
Side
3.18
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27
1.00 0.10
0.3 0.15
0.35 0.05
3.80
0.3~1.0
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
52
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
8.3 128Mx72 HMT112U7BFR8C 8.2 128Mx64 - HMT112U6BFR8C
Front
2.10 0.15 Min 1.45 SPD Max R0.70 30.00
4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50
Back
Side
3.18
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27
1.00 0.10
0.3 0.15
0.35 0.05
3.80
0.3~1.0
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
53
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
8.4 256Mx64 - HMT125U6BFR8C
Front
2.10 0.15 Min 1.45 SPD 4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50 Max R0.70 30.00
Back
Side
4.00
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27
1.00 0.10
0.3 0.15
0.35 0.05
3.80
0.3~1.0
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
54
HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C
8.5 256Mx72 - HMT125U7BFR8C
Front
2.10 0.15 Min 1.45 SPD Max R0.70 30.00
4x3.00 0.10 17.30 DETAIL-A 2x2.30 0.10 5.175 47.00 128.95 133.35 71.00 DETAIL-B 2x2.50 0.10 9.50
Back
Side
4.00
Detail - A
0.80 0.05
Detail - B
2.50 FULL R
2.50 0.20
1.27
1.00 0.10
0.3 0.15
0.35 0.05
3.80
0.3~1.0
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
55

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